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Digital Power Monitor with Convert Pin and ALERTB Output ADM1191
FEATURES
Powered from 3.15 V to 26 V Precision current sense amplifier Precision voltage input 12-bit ADC for current and voltage readback Convert pin (CONV) for commanding an ADC read SETV input for setting overcurrent alert threshold ALERTB output provides an overcurrent interrupt I2C(R) fast mode-compliant interface (400 kHz maximum) Two address pins allow 16 devices on the same bus 10-lead MSOP
FUNCTIONAL BLOCK DIAGRAM
CONV
ADM1191
VCC V SDA 0 12-BIT ADC 1 MUX I2 C SCL A1 A0
A SENSE CURRENT SENSE AMPLIFIER
I
ALERT SETV COMPARATOR
ALERTB
APPLICATIONS
Power monitoring/power budgeting Central office equipment Telecommunication and data communication equipment PCs/servers
GND
Figure 1.
GENERAL DESCRIPTION
The ADM1191 is an integrated current sense amplifier that offers digital current and voltage monitoring via an on-chip, 12-bit analog-to-digital converter (ADC), communicated through an I2C interface. An internal current sense amplifier senses voltage across the sense resistor in the power path via the VCC pin and the SENSE pin. A 12-bit ADC can measure the current seen in the sense resistor, as well as the supply voltage on the VCC pin. An industry-standard I2C interface allows a controller to read current and voltage data from the ADC. Measurements can be initiated by an I2C command or via the convert (CONV) pin. The CONV pin is especially useful for synchronizing reads on multiple ADM1191 devices. Alternatively, the ADC can run continuously, and the user can read the latest conversion data whenever it is required. Up to 16 unique I2C addresses can be created, depending on the way the A0 pin and the A1 pin are connected. A SETV pin is also included. A voltage applied to this pin is internally compared to the output voltage on the current sense amplifier. The output of the SETV comparator asserts when the current sense amplifier ouput exceeds the SETV voltage. When this event occurs, the ALERTB output asserts.
3.15V TO 26V
RSENSE
VCC
SENSE ALERTB
CONTROLLER
INTERRUPT
ADM1191
SETV SDA SCL CONV A1 A0 SDA SCL
P = VI
CONV
Figure 2. Applications Diagram
The ALERTB output can be used as a flag to warn a microcontroller or field programmable gate array (FPGA) of an overcurrent condition. ALERTB outputs of multiple ADM1191 devices can be tied together and used as a combined alert. The ADM1191 is packaged in a 10-lead MSOP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05804-002
GND
05804-001
ADM1191 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Voltage and Current Readback ....................................................... 9 Serial Bus Interface....................................................................... 9 Identifying the ADM1191 on the I2C Bus..................................9 General I2C Timing.......................................................................9 Timing Diagrams ....................................................................... 10 Write and Read Operations ...................................................... 11 Quick Command........................................................................ 11 Write Command Byte ................................................................ 11 Write Extended Byte .................................................................. 12 Read Voltage and/or Current Data Bytes ................................ 13 ALERTB Output......................................................................... 14 SETV Pin ..................................................................................... 14 Kelvin Sense Resistor Connection ........................................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
9/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADM1191 SPECIFICATIONS
VCC = 3.15 V to 26 V; TA = -40C to +85C; typical values at TA = 25C, unless otherwise noted. Table 1.
Parameter VCC PIN Operating Voltage Range, VVCC Supply Current, ICC Undervoltage Lockout, VUVLO Undervoltage Lockout Hysteresis, VUVLOHYST CONV PIN Input Current, ICONV Logic Low Threshold, VCONVL Logic High Threshold, VCONVH MONITORING ACCURACY 1 Current Sense Absolute Accuracy Min 3.15 1.7 2.8 80 -2 1.4 -1.45 -1.8 -2.8 -5.7 -1.5 -1.8 -2.95 -6.1 -1.95 -2.45 -3.85 -6.7 VSENSE for ADC Full Scale 105.84 +1.45 +1.8 +2.8 +5.7 +1.5 +1.8 +2.95 +6.1 +1.95 +2.45 +3.85 +6.7 Typ Max 26 2 Unit V mA V mV A V mV % % % % % % % % % % % % mV VSENSE = 75 mV VSENSE = 50 mV VSENSE = 25 mV VSENSE = 12.5 mV VSENSE = 75 mV VSENSE = 50 mV VSENSE = 25 mV VSENSE = 12.5 mV VSENSE = 75 mV VSENSE = 50 mV VSENSE = 25 mV VSENSE = 12.5 mV 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +85C 0C to +85C 0C to +85C 0C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Conditions
VCC rising
+2 1.2
Voltage Accuracy
-0.85 -0.9 -0.85 -0.9 -0.9 -1.15
+0.85 +0.9 +0.85 +0.9 +0.9 +1.15 6.65 26.52
% % % % % % V V
VCC for ADC Full Scale, Low Range (VRANGE = 1) VCC for ADC Full Scale, High Range (VRANGE = 0) SENSE PIN Input Current, ISENSE
This is an absolute value to be used when converting ADC codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see specs for Current Sense Absolute Accuracy) 0C to +70C VCC = 3.0 V to 5.5 V (low range) 0C to +70C VCC = 10.8 V to 16.5 V (high range) 0C to +85C VCC = 3.0 V to 5.5 V (low range) 0C to +85C VCC = 10.8 V to 16.5 V (high range) VVCC = 3.0 V to 5.5 V -40C to +85C (low range) -40C to +85C VVCC = 10.8 V to 16.5 V (high range) These are absolute values to be used when converting ADC codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see specs for Voltage Accuracy) VSENSE = VVCC
-1
+1
A
Rev. 0 | Page 3 of 16
ADM1191
Parameter SETV PIN Overcurrent Trip Threshold Overcurrent Trip, Gain {VSETV/(VVCC - VSENSE)} Input Current, ISETVLEAK ALERTB PIN Output Low Voltage, VALERTOL Input Current, IALERT A0 PIN, A1 PIN Set Address to 00, VADRLOWV Set Address to 01, RADRLOWZ Set Address to 10, IADRHIGHZ Set Address to 11, VADRHIGHV Input Current for 00 Decode, IADRLOW Input Current for 11 Decode, IADRHIGH I2C TIMING Low Level Input Voltage, VIL High Level Input Voltage, VIH Low Level Output Voltage on SDA, VOL Output Fall Time on SDA from VIHMIN to VILMAX Maximum Width of Spikes Suppressed by Input Filtering on SDA and SCL Pins Input Current, II, on SDA/SCL When Not Driving Out a Logic Low Input Capacitance on SDA/SCL SCL Clock Frequency, fSCL Low Period of the SCL Clock High Period of the SCL Clock Setup Time for Repeated Start Condition, tSU;STA SDA Output Data Hold Time, tHD;DAT Setup Time for a Stop Condition, tSU;STO Bus Free Time Between a Stop and a Start Condition, tBUF Capacitive Load for Each Bus Line
1
Min 98 49.5 -1
Typ 100 50 18
Max 102 50.5 +1
Unit mV mV A V mA A V k A V A A V V V ns ns A pF kHz ns ns ns ns ns ns pF
Conditions VSETV = 1.8 V VSETV = 0.9 V VSETV = 0.9 V to 1.9 V VSETV = 0.9 V to 1.9 V IALERT = -100 A IALERT = -2 mA VALERT = VCC; ALERTB not asserted Low state Resistor to ground state, load pin with specified resistance for 01 decode Open state, maximum load allowed on A0 pin or A1 pin for 10 decode High state VADR = 2.0 V to 5.5 V VADR = 0 V to 0.8 V
0.05 1 -1 0 80 -0.3 2 -40 3 -25
0.1 1.5 +1 0.8 160 +0.3 5.5 6
120
0.3 VBUS 0.7 VBUS 20 + 0.1 CB 50 -10 5 400 600 1300 600 100 600 1300 0.4 250 250 +10
IOL = 3 mA CB = bus capacitance from SDA to GND
900
400
Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC error, and error in ADC full-scale code conversion factor.
Rev. 0 | Page 4 of 16
ADM1191 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC Pin SENSE Pin CONV Pin SETV Pin ALERTB Pin SDA Pin, SCL Pin A0 Pin, A1 Pin Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 30 V 30 V -0.3 V to +6 V 30 V 30 V -0.3 V to +6 V -0.3 V to +6 V -65C to +125C -40C to +85C 300C 150C
THERMAL CHARACTERISTICS
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type 10-Lead MSOP JA 137.5 Unit C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 5 of 16
ADM1191 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADM1191ARMZ
VCC 1 SENSE 2 CONV 3 GND 4 SETV 5 TOP VIEW (Not to Scale)
10 9 8 7 6
ALERTB A1 A0
05804-003
SDA SCL
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 Mnemonic VCC SENSE Description Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 26 V. An undervoltage lockout (UVLO) circuit resets the ADM1191 when a low supply voltage is detected. Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin generates a voltage across a sense resistor. This voltage is proportional to the load current. A current sense amplifier amplifies this voltage before it is digitized by the ADC. Convert Start Pin. A high level on this pin enables an ADC conversion. The state of an internal control register, which is set through the I2C interface, configures the part to convert current only, voltage only, or both channels when the convert pin is asserted. Chip Ground Pin. Input Pin. The voltage driven onto this pin is compared to the output of the internal current sense amplifier. The lower the voltage on the SETV, the lower the current level that causes the ALERTB output to assert. I2C Clock Pin. Open-drain input; requires an external resistive pull-up. I2C Data I/O Pin. Open-drain input/output; requires an external resistive pull-up. I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor. Sixteen different I2C address options are available, depending on the external configuration of the A0 pin and the A1 pin. I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor. Sixteen different I2C address options are available, depending on the external configuration of the A0 pin and the A1 pin. Alert Output Pin. Active-low, open-drain configuration. This pin asserts low when an overcurrent condition is present. The level at which an overcurrent condition is detected depends on the voltage on the SETV pin.
3
CONV
4 5 6 7 8 9 10
GND SETV SCL SDA A0 A1 ALERTB
Rev. 0 | Page 6 of 16
ADM1191 TYPICAL PERFORMANCE CHARACTERISTICS
1000 2.0 900 1.8 1.6 1.4
HITS PER CODE (1000 READS)
800 700 600 500 400 300 200 100
ICC (mA)
1.2 1.0 0.8 0.6 0.4 0.2 0 4 8 12 16 20 24 28
05804-021
0
2046
2047
2048 CODE
2049
2050
VCC (V)
Figure 4. Supply Current vs. Supply Voltage
Figure 7. ADC Noise, Current Channel, Midcode Input, 1000 Reads
1000
2.0
900
1.8 1.6 1.4 ICC (mA) 1.2 1.0 0.8 0.6 0.4
100
HITS PER CODE (1000 READS)
800 700 600 500 400 300 200
0.2 -20 0 20 40 60 80
05804-022
0 -40
779
780
781 CODE
782
783
TEMPERATURE (C)
Figure 5. Supply Current vs. Temperature
Figure 8. ADC Noise, 14:1 Voltage Channel, 5 V Input, 1000 Reads
1000 900
3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
11 DECODE
10 DECODE
01 DECODE 00 DECODE
HITS PER CODE (1000 READS)
800 700 600 500 400 300 200 100 3078 3079 3080 CODE 3081 3082
05804-062
V (A0/A1)
0
-30
-25
-20
-15
-10
-5
0
5
10
I (A0/A1) (A)
Figure 6. Address Pin Voltage vs. Address Pin Current for Four Addressing Options
05804-026
0 -35
Figure 9. ADC Noise, 7:1 Voltage Channel, 5 V Input, 1000 Reads
Rev. 0 | Page 7 of 16
05804-061
0
05804-060
0
ADM1191
4 3 0.50 2 1
INL (LSB)
0.60 0.55
0.45 ALERTB LOW (V)
05804-023
0.40 0.35 0.30 0.25 0.20 0.15 0.10
0 -1 -2 -3
0.05 0 500 1000 1500 2000 CODE 2500 3000 3500 4000 -20 0 20 40 60 80
05804-047
-4
0 -40
TEMPERATURE (C)
Figure 10. INL for ADC
Figure 13. ALERTB Output Low Voltage vs. Temperature @ 1 mA
4 3
1.0
0.8
2 1 0 -1 -2
0.2
OUTPUT LOW (V)
DNL (LSB)
0.6
0.4
-3
05804-048 05804-049
05804-024
-4
0
0
500
1000
1500
2000 CODE
2500
3000
3500
4000
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
VCC (V)
Figure 11. DNL for ADC
Figure 14. ALERTB Output Low Voltage vs. Supply @ 1 mA
2.0 1.8 1.6 1.4
OUTPUT LOW (V)
100 90 80 70
VLIM (mV)
60 50 40 30 20 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
05804-046
1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 LOAD CURRENT (mA)
0
VSETV (V)
Figure 12. VLIM vs. VSETV
Figure 15. ALERTB Output Low Voltage vs. Load Current
Rev. 0 | Page 8 of 16
ADM1191 VOLTAGE AND CURRENT READBACK
The ADM1191 contains the components to allow voltage and current readback over an Inter-IC (I2C) bus. The voltage output of the current sense amplifier and the voltage on the VCC pin are fed into a 12-bit ADC via a multiplexer. The device can be instructed to convert voltage and/or current at any time during operation via an I2C command or by driving the CONV pin high. When all conversions are complete, the voltage and/or current values can be read out to 12-bit accuracy in two or three bytes. 1. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCL, remains high. This indicates that a data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7bit slave address (MSB first) plus an R/W bit that determines the direction of the data transfer; that is, whether data is written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from it or written to it. If the R/W bit is 0, the master writes to the slave device. If the R/W bit is 1, the master reads from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-tohigh transition when the clock is high can be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It can be an instruction, such as telling the slave device to expect a block write, or it can be a register address that tells the slave where subsequent data is to be written. Because data can flow in only one direction, as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as a no acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition.
SERIAL BUS INTERFACE
Control of the ADM1191 is carried out via the serial system management bus (I2C). This interface is compatible with I2C fast mode (400 kHz maximum). The ADM1191 is connected to this bus as a slave device, under the control of a master device.
IDENTIFYING THE ADM1191 ON THE I2C BUS
The ADM1191 has a 7-bit serial bus slave address. When the device powers up, it does so with a default serial bus address. The three MSBs of the address are set to 010; the four LSBs are determined by the state of the A0 pin and the A1 pin. There are 16 different configurations available on the A0 pin and A1 pin that correspond to 16 different I2C addresses for the four LSBs (see Table 5). This scheme allows 16 ADM1191 devices to operate on a single I2C. Table 5. Setting I2C Addresses via the A0 Pin and the A1 Pin
A0 Configuration Low state Low state Low state Low state Resistor to GND Resistor to GND Resistor to GND Resistor to GND Floating Floating Floating Floating High state High state High state High state A1 Configuration Low state Resistor to GND Floating High state Low state Resistor to GND Floating High state Low state Resistor to GND Floating High state Low state Resistor to GND Floating High state Address 0x60 0x68 0x70 0x78 0x62 0x6A 0x72 0x7A 0x64 0x6C 0x74 0x7C 0x66 0x6E 0x76 0x7E
GENERAL I2C TIMING
Figure 16 and Figure 17 show timing diagrams for general read and write operations using the I2C. The I2C specification defines conditions for different types of read and write operations, which are discussed later. The general I2C protocol operates as follows:
Rev. 0 | Page 9 of 16
ADM1191
TIMING DIAGRAMS
1 SCL SDA 0 1 0 1 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 ACKNOWLEDGE BY SLAVE 9 9 1 9
START BY MASTER FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2
ACKNOWLEDGE BY SLAVE 9 1
FRAME 2 COMMAND CODE
D1
D0
D7
D6
D5
D4
D3
D2
D1
FRAME 3 DATA BYTE
FRAME N DATA BYTE
Figure 16. General I2C Write Timing Diagram
1 SCL SDA 0 1 0 1 1 A1 A0 R/W
9
1
9
D7
D6
D5
D4
D3
D2
D1
D0 ACKNOWLEDGE BY MASTER 9
START BY MASTER FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2
ACKNOWLEDGE BY SLAVE 9 1
FRAME 2 DATA BYTE
D1
D0
D7
D6
D5
D4
D3
D2
D1
FRAME 3 DATA BYTE
FRAME N DATA BYTE
Figure 17. General I C Read Timing Diagram
2
tLOW
SCL
tR
tF
tHD;STA
tHD;STA
tHIGH tHD;DAT tSU;DAT
tSU;STA
tSU;STO
SDA S
P
S
P
Figure 18. Serial Bus Timing Diagram
Rev. 0 | Page 10 of 16
05804-006
tBUF
05804-005
ACKNOWLEDGE BY MASTER
D0 NO ACKNOWLEDGE STOP BY MASTER
05804-004
ACKNOWLEDGE BY SLAVE
D0 ACKNOWLEDGE BY STOP BY SLAVE MASTER
ADM1191
WRITE AND READ OPERATIONS
The I C specification defines several protocols for different types of read and write operations. The operations used in the ADM1191 are discussed in the sections that follow. Table 6 shows the abbreviations used in the command diagrams. Table 6. I2C Abbreviations
Abbreviation S P R W A N Condition Start Stop Read Write Acknowledge No acknowledge
2
WRITE COMMAND BYTE
In the write command byte operation, the master device sends a command byte to the slave device, as follows: 1. 2. 3. 4. The master device asserts a start condition on SDA. The master sends the 7-bit slave address, followed by the write bit (low). The addressed slave device asserts an acknowledge on SDA. The master sends the command byte. The command byte is identified by an MSB = 0. An MSB =1 indicates an extended register write (see the Write Extended Byte section). The slave asserts an acknowledge on SDA. The master asserts a stop condition on SDA to end the transaction.
1 2 3 4 56
05804-008
QUICK COMMAND
The quick command operation allows the master to check if the slave is present on the bus, as follows: 1. 2. 3. The master device asserts a start condition on SDA. The master sends the 7-bit slave address, followed by the write bit (low). The addressed slave device asserts an acknowledge on SDA.
1 2 3
05804-007
5. 6.
SLAVE COMMAND S ADDRESS W A AP BYTE
Figure 20. Write Command Byte
SLAVE S ADDRESS W A
The seven LSBs of the command byte are used to configure and control the ADM1191. Table 7 provides details of the function of each bit.
Figure 19. Quick Command
Table 7. Command Byte Operations
Bit C0 C1 C2 C3 C4 Default 0 0 0 0 0 Name V_CONT V_ONCE I_CONT I_ONCE VRANGE Function Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the ADM1191 asserts an acknowledge and returns all 0s in the returned data. Set to convert voltage once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC conversion is complete. Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the ADM1191 asserts an acknowledge and returns all 0s in the returned data. Set to convert current once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC conversion is complete. Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1 voltage divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the VCC pin for an ADC full-scale result is 26.52 V for VRANGE = 0 and 6.65 V for VRANGE = 1. Unused, Status Read. When this bit is set, the data byte read back from the ADM1191 is the STATUS byte. It contains the status of the device alerts. See Table 15 for full details of the STATUS byte.
C5 C6
0 0
N/A STATUS_RD
Rev. 0 | Page 11 of 16
ADM1191
WRITE EXTENDED BYTE
In the write extended byte operation, the master device writes to one of the three extended registers of the slave device, as follows: 1. 2. 3. 4. The master device asserts a start condition on SDA. The master sends the 7-bit slave address, followed by the write bit (low). The addressed slave device asserts an acknowledge on SDA. The master sends the register address byte. The MSB of this byte is set to 1 to indicate an extended register write. The two LSBs indicate which of the three extended registers is to be written to (see Table 8). All other bits should be set to 0. The slave asserts an acknowledge on SDA. The master sends the command byte. The command byte is identified by an MSB = 0. An MSB = 1 indicates an extended register write. 7. 8. The slave asserts an acknowledge on SDA. The master asserts a stop condition on SDA to end the transaction.
1 2 3 4 5 6 78
05804-009
SLAVE REGISTER REGISTER S ADDRESS W A ADDRESS A AP DATA
Figure 21. Write Extended Byte
Table 9, Table 10, and Table 11 give details of each extended register. Table 8. Extended Register Addresses
A6 0 0 0 A5 0 0 0 A4 0 0 0 A3 0 0 0 A2 0 0 0 A1 0 1 1 A0 1 0 1 Extended Register ALERT_EN ALERT_TH CONTROL
5. 6.
Table 9. ALERT_EN Register Operations
Bit 0 1 2 3 4 Default 0 0 1 0 0 Name EN_ADC_OC1 EN_ADC_OC4 EN_OC_ALERT EN_OFF_ALERT CLEAR Function Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH register. Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the ALERT_TH register. Enables the OC_ALERT register. If an overcurrent condition is present, the OC_ALERT register captures and latches this condition. N/A. Clears the ON_ALERT, OC_ALERT, and ADC_ALERT status bits in the status register. These can immediately reset if the source of the alert has not been cleared or disabled with the other bits in this register. This bit self-clears to 0 after the status register bits have been cleared.
Table 10. ALERT_TH Register Operations
Bit 7:0 Default FF Function The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit number corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit 0 Default 0 Name SWOFF Function Forces the ALERTB pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).
Rev. 0 | Page 12 of 16
ADM1191
READ VOLTAGE AND/OR CURRENT DATA BYTES
The ADM1191 can be set up to provide information in three different ways (see the Write Command Byte section). Depending on how the device is configured, the following data can be read out of the device after a conversion (or conversions). For cases where the master is reading voltage only or current only, only two data bytes are read. Step 7 and Step 8 are not required.
1 2 3 4 5 6 7 8 9 10
05804-010
Voltage and Current Readback
The ADM1191 digitizes both voltage and current. Three bytes are read out of the device in the format shown in Table 12. Table 12. Voltage and Current Readback
Byte 1 2 3 Contents Voltage MSBs Current MSBs LSBs B7 V11 I11 V3 B6 V10 I10 V2 B5 V9 I9 V1 B4 V8 I8 V0 B3 V7 I7 I3 B2 V6 I6 I2 B1 V5 I5 I1 B0 V4 I4 I0
SLAVE S ADDRESS R A DATA 1 A DATA 2 A DATA 3 N P
Figure 22. Three-Byte Read from ADM1191
1 2 3 4 5 6 78
05804-011
SLAVE REGISTER REGISTER S ADDRESS R A ADDRESS A NP DATA
Figure 23. Two-Byte Read from ADM1191
Converting ADC Codes to Voltage and Current Readings
The following equations can be used to convert ADC codes representing voltage and current from the ADM1175 12-bit ADC into actual voltage and current values. Voltage = (VFULLSCALE/4096) x Code where: VFULLSCALE = 6.65 (7:2 range) or 26.52 (14:1 range). Code is the ADC voltage code read from the device (Bit V0 to Bit V11). Current = ((IFULLSCALE/4096) x Code)/Sense Resistor where: IFULLSCALE = 105.84 mV. Code is the ADC current code read from the device (Bit I0 to Bit I11).
Voltage Readback
The ADM1191 digitizes voltage only. Two bytes are read out of the device in the format shown in Table 13. Table 13. Voltage Only Readback Format
Byte Contents 1 Voltage MSBs 2 Voltage LSBs B7 B6 B5 B4 B3 B2 V11 V10 V9 V8 V7 V6 V3 V2 V1 V0 0 0 B1 V5 0 B0 V4 0
Current Readback
The ADM1191 digitizes current only. Two bytes are read out of the device in the format shown in Table 14. Table 14. Current Only Readback Format
Byte Contents 1 Current MSBs 2 Current LSBs B7 I11 I3 B6 I10 I2 B5 B4 B3 B2 I9 I8 I7 I6 I1 I0 0 0 B1 I5 0 B0 I4 0
Read Status Register
A single register of status data can also be read from the ADM1191. 1. 2. 3. 4. 5. The master device asserts a start condition on SDA. The master sends the 7-bit slave address, followed by the read bit (high). The addressed slave device asserts an acknowledge on SDA. The master receives the status byte. The master asserts an acknowledge on SDA.
1 2 3 4 5
05804-012
The following series of events occurs when the master receives three bytes (voltage and current data) from the slave device: 1. 2. 3. 4. 5. 6. 7. 8. 9. The master device asserts a start condition on SDA. The master sends the 7-bit slave address, followed by the read bit (high). The addressed slave device asserts an acknowledge on SDA. The master receives the first data byte. The master asserts an acknowledge on SDA. The master receives the second data byte. The master asserts an acknowledge on SDA. The master receives the third data byte. The master asserts a no acknowledge on SDA.
SLAVE S ADDRESS R A DATA 1 A
Figure 24. Status Read from ADM1191
10. The master asserts a stop condition on SDA, and the transaction ends.
Table 15 shows the ADM1191 status registers in detail. Note that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 of the ALERT_EN register (CLEAR).
Rev. 0 | Page 13 of 16
ADM1191
Table 15. Status Byte Operations
Bit 0 1 2 3 4 5 Name ADC_OC ADC_ALERT OC OC_ALERT OFF_STATUS OFF_ALERT Function An ADC-based overcurrent comparison has been detected on the last three conversions. An ADC-based overcurrent trip has occurred, which has caused the alert. Cleared by writing to Bit 4 of the ALERT_EN register. An overcurrent condition is present (that is, the output of the current sense amplifier is greater than the voltage on the SETV input). An overcurrent condition has caused the ALERT block to latch a fault, and the ALERTB output has asserted. Cleared by writing to Bit 4 of the ALERT_EN register. Set to 1 by writing to the SWOFF bit of the CONTROL register. An alert has been caused by the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register.
RSENSE ILOAD
ALERTB OUTPUT
The ALERTB output is an open-drain pin with 30 V tolerance. This output can be used as an overcurrent flag by connecting it to the general-purpose logic input of a controller. Under normal operation, this output is pulled high (an external pull-up resistor should be used because this is an open-drain pin). When an overcurrent condition occurs, the ADM1191 pulls this output low.
3.15V TO 26V RSENSE
VCC
SENSE
ADM1191
A CURRENT SENSE AMPLIFIER
APPLIED VOLTAGE SETV
VCC SENSE ALERTB
ALERT COMPARATOR
ALERT
05804-014
CONTROLLER
ALERTB
ADM1191
SETV SDA SCL CLRB TIMER SDA SCL CLRB
P = VI
Figure 26. SETV Operation
KELVIN SENSE RESISTOR CONNECTION
When using a low value sense resistor for high current measurement, the problem of parasitic series resistance can arise. The lead resistance can be a substantial fraction of the rated resistance, making the total resistance a function of lead length. This problem can be avoided by using a Kelvin sense connection. This type of connection separates the current path through the resistor and the voltage drop across the resistor. Figure 27 shows the correct way to connect the sense resistor between the VCC pin and the SENSE pin of the ADM1191.
SENSE RESISTOR
05804-013
GND
ADR
Figure 25. Using the ALERTB Output as an Interrupt
SETV PIN
The SETV pin allows the user to adjust the current level that trips the ALERTB output. The output of the current sense amplifier is compared with the voltage driven onto the SETV pin. If the current sense amplifier output is higher than the SETV voltage, then the output of the comparator asserts. By driving a different voltage onto the SETV pin, the ADM1191 detects an overcurrent condition at a different current level, with a gain of 18. See Figure 15 for an illustration of this relationship.
CURRENT FLOW FROM SUPPLY
CURRENT FLOW TO LOAD
KELVIN SENSE TRACES
VCC
SENSE
05804-015
ADM1191
Figure 27. Kelvin Sense Connections
Rev. 0 | Page 14 of 16
ADM1191 OUTLINE DIMENSIONS
3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8 0 0.80 0.60 0.40
10 6
5.15 4.90 4.65
1
5
SEATING PLANE
0.23 0.08
Figure 28. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model ADM1191-2ARMZ-R7 1 EVAL-ADM1191EBZ1
1
Temperature Range -40C to +85C
Package Description 10-Lead MSOP Evaluation Board
Package Option RM-10
Branding M5L
Z = Pb-free part.
Rev. 0 | Page 15 of 16
ADM1191 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05804-0-9/06(0)
Rev. 0 | Page 16 of 16

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